HDI PCB Support Higher Pin Count Components

With the increasing miniaturization of electronic devices, PCBs have to be fabricated in smaller areas. This has been made possible by HDI technology, which allows for more pathways in the same or smaller area of the board. The increased routing space and the ability to use thinner traces also reduces impedance, reduces EMI, increases signal quality and improves thermal management. The HDI PCB is now found in a wide variety of gadgets, from mobile phones to smart watches and wearables. However, the technology is moving even further toward the microchip level and with it will come new challenges for designers.

To support these new chip sizes, the hdi pcb design will have to be updated with different routing strategies, via escape patterns and component package sizes. The smaller component packages and pin pitches will require different routing widths which impact the layout and the via types used. This also affects the layer stackup configuration. The choice of a fabrication house is crucial as they must be ready to support the latest technologies and be able to provide the high-density design features required.

There are various constructions used in HDI, ranging from the simple to the complex. The most common is the i+N+i (or i+3+N) construction. This uses i sequentially laminated layers with i+N+i microvias. Other variations include the i+N+2 construction, which has two additional inner layers. The most complex is the i+N+6 or every layer interconnect (ELIC) construction. This has six additional inner layers.

How Does HDI PCB Support Higher Pin Count Components?

Unlike through-hole vias, which connect the outer layers with the inner ones, HDI vias connect the inner layers directly with each other without passing through the outer layer surfaces. These are known as blind or buried vias. Unlike through-holes, which can be plated over with solder, buried vias are drilled through the entire board thickness and are visible on one side only.

The other type of HDI via is the skipped or staggered via, which is a via hole that only passes through the layers above and below it in the stackup. Skipped vias are arranged in an “X” pattern, with two or more holes in a row that skip each other by one layer. Staggered vias are arranged in an “X” or “Y” pattern with one or more skipped vias in each column. Another option is the so-called landless via technology, which is a laser-drilled hole that connects only pads and does not pass through the layer stack.

These can be plated with hard gold or ENEPIG. A good surface finish is essential for HDI to avoid oxidation and maintain solderability between the components and the copper. Achieving these advanced features requires new technology and equipment that many manufacturers are not yet prepared to implement. It is also necessary to develop new automated optical inspection and test methods to verify the accuracy of these ultra-thin foils. This is not an easy task, but it is important for the future of electronics and the development of new and exciting devices.